The invention relates to a liquid crystal display and fabrication method thereof, and more particularly to a liquid crystal display without storage capacitance electrode lines.
Generally, a liquid crystal display (LCD) comprises a lower substrate, an upper substrate and a liquid crystal layer interposed therebetween. The upper substrate typically comprises a color filter and a common electrode. The lower substrate typically comprises a plurality of pixel areas defined by crossing gate lines and source lines (or data lines). Each pixel area comprises a thin film transistor serving as a switching element located near the intersection of the gate and source lines and a pixel electrode electrically connected to the thin film transistor. The thin film transistor comprises a gate, a source and a drain, wherein the gate is typically an extended portion of the gate line and the drain is electrically connected to the pixel electrode via a contact hole. The liquid crystal layer interposed between the common electrode and the pixel electrode forms a capacity of liquid crystal (referred to in the following as CLC).
In order to improve image quality, a storage capacitor (referred to in the following as Cs) must be formed in each pixel area. FIG. 1A is a partial top view of a conventional array substrate. FIG. 1B shows a cross-section view taken along line 1B-1B of FIG. 1A. In FIGS. 1A and 1B, a transversely extended gate line 110 and a storage capacitance electrode line 120 (referred to in the following as Cs lines 120) are formed on a glass substrate 100. The gate line 110 comprises a protrusion 115 serving as a gate 115. A gate insulating layer 130 is then formed covering the entire substrate 100. A semiconductor 140 is formed on part of the gate insulating layer 130. A longitudinally extended source line 150 and a discrete metal layer 155 are formed on part of the insulating layer 130. The source line 150 comprises a source 152 extended onto part of the semiconductor layer 140. Simultaneously, a drain 154 is formed on part of the semiconductor layer 140 and is extended onto part of the gate insulating layer 130.
An insulating layer 160 is then formed covering the entire substrate 100. A first opening 172 and a second opening 174 penetrating the insulating layer 160 are formed to expose the drain 154 and the metal layer 155 respectively. A pixel electrode 180 is formed on part of the insulating layer 160 and fills the openings 172 and 174 to electrically connect the drain 154 and the metal layer 155. Accordingly, the metal layer 155, the Cs line 120 and the gate insulating layer 130 interposed therebetween constitute a Cs 199.
Nevertheless, the conventional LCD has some drawbacks. For example, the entire LCD panel must be discarded due to abnormal bright lines when the Cs line 120 is broken 190. Additionally, since the Cs line 120 is opaque, the aperture ratio of a pixel is reduced resulting inferior pixel quality. Furthermore, cross-talk may occur at the intersection of the Cs line 120 and the source line 150, degrading display quality.
U.S. Pat. No. 6,172,728 to Hiraishi, the entirety of which is hereby incorporated by reference, describes a reflective LCD including address lines shaped to reduce parasitic capacitance. The address lines of the reflective LCD have bends, notches, protrusions and holes, thereby improving light efficiency and minimizing parasitic capacitance.
U.S. Pat. No. 6,404,465 to Nakayama et al., the entirety of which is hereby incorporated by reference, describes an array substrate of an LCD. In the array substrate, Cs lines overlap an upper region of source lines and pixel electrodes overlap an upper region of the Cs lines.